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| TECHNICAL DATA IN74LV164 8-BIT SERIAL-IN/PARALLEL-OUT SHIFT REGISTER The IN74LV164 is a low-voltage Si-gate CMOS device and is pin and function compatible with the IN74HC/HCT164. The IN74LV164 is an 8-bit edge-triggered shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (DSA or DSB); either input can be used as an active HIGH enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied HIGH. Data shifts one place to the right on each LOW-to-HIGH transition of the clock (CP) input and enters into Q0, which is the logical AND of the two data inputs (DSA, DSB ) that existed one set-up time prior to the rising clock edge. A LOW on the master reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all outputs LOW. * * * * * Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 1.2 to 5.5 V Low Input Current: 1.0 A, 0.1 A at O = 25 N Output Current: 6 mA at VCC = 3.0 V; 12 mA at VCC = 4.5 V High Noise Immunity Characteristic of CMOS Devices N SUFFIX PLASTIC DIP 14 1 14 1 ORDERING INFORMATION D SUFFIX SO IN74LV164N IN74LV164D IZ74LV164 Plastic DIP SOIC chip TA = -40 to 125 C for all packages PIN ASSIGNMENT DSA 1 DSB 2 3 4 5 6 7 14 13 12 11 10 9 8 V CC Q7 Q6 Q5 Q4 MR CP LOGIC DIAGRAM Q0 Q1 1 SERIAL DSA DATA 2 INPUTS DSB Q2 2 Q0 DATA 4 Q1 Q3 GND PARALLEL DATA OUTPUTS 5 Q2 6 Q3 10 Q 4 11 Q 5 12 Q 6 CP 8 13 Q 7 FUNCTION TABLE Inputs Outputs DSB X L H L H Q0 L L L L H Q1 ... Q7 L...L Q0 ... Q6 Q0 ... Q6 Q0 ... Q6 Q0 ... Q6 MR L H CP X DSA X L L H H MR 9 PIN 14=VCC PIN 7 = GND H H H H = high voltage level L = low voltage level X = don't care INTEGRAL 1 IN74LV164 MAXIMUM RATINGS * Symbol VCC IIK * 1 2 Parameter DC supply voltage DC Input diode current DC Output diode current DC Output source or sink current VCC current GND current Power dissipation per package: * Plastic DIP SO Storage Temperature Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO Package) from Case for 4 Seconds 4 Value -0.5 to + 7.0 20 50 25 50 50 750 500 -65 to +150 260 Unit V mA mA mA mA mA mW IOK * IO * ICC IGND PD 3 Tstg TL * C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. * 1 VI < -0.5 V or VI > VCC + 0.5 V. * 2 VO < -0.5 V or VO > VCC + 0.5 V. * 3 -0.5 V < VO < VCC + 0.5 V. * 4 Derating - Plastic DIP: - 12 mW/C from 70 to 125C SO Package: : - 8 mW/C from 70 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO TA tr, t f DC Supply Voltage Input Voltage Output Voltage Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) 1.0 V VCC < 2.0 V 2.0 V VCC < 2.7 V 2.7 V VCC < 3.6 V 3.6 V VCC 5.5 V Parameter Min 1.2 0 0 -40 0 0 0 0 Max 5.5 VCC VCC +125 500 200 100 50 Unit V V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. INTEGRAL 2 IN74LV164 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Test Symbol Parameter conditions VCC V Guaranteed Limit 25C to -40C min VIH HIGH level input voltage 1.2 2.0 2.7 3.0 3.6 4.5 5.5 1.2 2.0 2.7 3.0 3.6 4.5 5.5 VI = VIH or VIL IO = -100 A 1.2 2.0 2.7 3.0 3.6 4.5 5.5 3.0 4.5 1.2 2.0 2.7 3.0 3.6 4.5 5.5 3.0 4.5 5.5 5.5 2.7 3.6 0.9 1.4 2.0 2.0 2.0 3.15 3.85 1.05 1.85 2.55 2.85 3.45 4.35 5.35 2.48 3.70 max 0.3 0.6 0.8 0.8 0.8 1.35 1.65 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.33 0.40 0.1 8.0 0.2 85C min 0.9 1.4 2.0 2.0 2.0 3.15 3.85 1.0 1.8 2.5 2.8 3.4 4.3 5.3 2.40 3.60 max 0.3 0.6 0.8 0.8 0.8 1.35 1.65 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.4 0.55 1.0 80 0.5 125C min 0.9 1.4 2.0 2.0 2.0 3.15 3.85 1.0 1.8 2.5 2.8 3.4 4.3 5.3 2.20 3.50 max 0.3 0.6 0.8 0.8 0.8 1.35 1.65 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.5 0.65 1.0 160 0.85 V Unit VIL LOW level input voltage V VOH HIGH level output voltage V VI = VIH or VIL IO = -6.0 mA VI = VIH or VIL IO = -12.0 mA VOL LOW level output voltage VI = VIH or VIL IO = 100 A V V V VI = VIH or VIL IO = 6.0 mA VI = VIH or VIL IO = 12.0 mA II ICC ICC1 Input current Supply current Supply current VI = VCC or 0 V VI =VCC or 0 V IO = 0 A VI =VCC - 0.6 V V V A A mA INTEGRAL 3 IN74LV164 AC ELECTRICAL CHARACTERISTICS (CL=50 pF, t r=t f= 2.5 ns, RL = 1 k) Test Symbol Parameter conditions VCC V Guaranteed Limit 25C to -40C min tPHL, tPLH Propagation delay , CP to Qn VI = 0 V or V1 Figure 1 and 4 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 5.0 VI = 0 V or VCC 5.5 100 28 21 17 14 60 19 13 11 9 50 5 5 5 5 70 15 11 9 8 max 150 30 23 18 15 150 30 23 18 15 2 16 22 27 32 7.0 80 85C min 130 34 25 20 17 80 22 16 13 11 50 5 5 5 5 100 19 14 11 10 max 180 39 29 23 19 180 39 29 23 19 1 14 19 24 27 125C min 160 41 30 24 20 100 26 19 15 13 50 5 5 5 5 130 24 18 14 12 max 210 49 36 29 24 210 49 36 29 24 1 12 16 20 24 ns Unit tPHL Propagation delay , MR to VI = 0 V or V1 Qn Figure 1 and 4 ns tw Pulse Width, CP or MR VI = 0 V or V1 Figure 1 ns tsu Setup Time, DSA or DSB to CP VI = 0 V or V1 Figure 3 ns th Hold Time, DSA or DSB to VI = 0 V or V1 CP Figure 3 ns trec Recovery Time, MR to CP VI = 0 V or V1 Figure 2 ns fmax Clock Frequency VI = 0 V or V1 Figure 1 and 4 MHz CI CPD Input capacitance Power dissipation capacitance pF pF INTEGRAL 4 IN74LV164 tw tr CP 10% VM (1 ) tf 90% V1 (2) MR t PHL Q VM (1) V1 (2) GND VOH VOL GND tw 1/fmax tPLH t PHL V OH V OL VM ( 1) Q VM (1 ) t rec CP VM (1) V1 (2) GND Figure 1. Switching Waveforms Figure 2. Switching Waveforms TEST POINT VALID DSA or DSB VM (1 ) V1 (2 ) GND t su th V1 VM ( 1) DEVICE UNDER TEST OUTPUT RL * (2 ) CL CP GND * Includes all probe and jig capacitance Figure 3. Switching Waveforms Note: (1) Figure 4. Test Circuit VM = 1.5 V at VCC = 2.7 V VM = 0.5 VCC at VCC =1.2 V, 2.0 V, 3.0 V, 4.5 V V1 = VCC at VCC =1.2 V, 2.0 V, 2.7 V, 4.5 V V1 = 2.7 V at VCC = 3.0 V (2) TIMING DIAGRAM CP DSA DSB MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 INTEGRAL 5 IN74LV164 CHIP PAD DIAGRAM 06 09 1.1+ 0.03 10 11 12 14 13 Y (0,0) X 1.71 + 0.03 Chip marking LV164 01 08 07 05 04 03 02 Location of marking (mm): left lower corner x= 0.960, y= 0.130. Chip thickness: 0.46 0.02 (0.35 0.02) mm. PAD LOCATION Location (left lower corner), mm Pad No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 Symbol DSA DSB Q0 Q1 Q2 Q3 GND CP MR Q4 Q5 Q6 Q7 VCC X 1.172 1.486 1.486 1.486 1.486 1.486 0.978 0.440 0.127 0.127 0.127 0.127 0.127 0.635 Y 0.131 0.131 0.363 0.531 0.689 0.885 0.885 0.885 0.885 0.653 0.485 0.326 0.131 0.131 Pad size, mm 0.100 o 0.100 0.100 o 0.100 0.100 o 0.100 0.100 o 0.100 0.100 o 0.100 0.100 o 0.100 0.100 o 0.100 0.100 o 0.100 0.100 o 0.100 0.100 o 0.100 0.100 o 0.100 0.100 o 0.100 0.100 o 0.100 0.100 o 0.100 Note: Pad location is given as per passivation layer INTEGRAL 6 |
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